RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
corresponding receive link is unchannelised. The E1 register bit is ignored. RCLK[n] is
gapped during non-data bytes. All data bits are treated as a contiguous stream with arbitrary
byte alignment.
E1:
The E1 frame structure select bit (E1) configures the corresponding receive link for
channelised E1 operation when CEN is set high. RCLK[n] is held quiescent during the FAS
and NFAS framing bytes. The data bit on RD[n] clocked in by the first rising edge of RCLK[n]
after an extended quiescent period is considered to be the most significant bit of time-slot 1.
Link data is present at time-slots 1 to 31. When E1 is set low and CEN is set high, the
corresponding receive link is configured for channelised T1 operation. RCLK[n] is held
quiescent during the framing bit. The data bit on RD[n] clocked in by the first rising edge of
RCLK[n] after an extended quiescent period is considered to be the most significant bit of
time-slot 1. Link data is present at time-slots 1 to 24. E1 is ignored when CEN is set low.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PMC [ PMC-SIERRA, INC ]
