RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x100 : RCAS Indirect Link and Time-slot Select
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
R
BUSY
RWB
X
0
X
0
0
0
0
0
X
X
X
0
0
0
0
0
R/W
Unused
R/W
R/W
R/W
R/W
R/W
Reserved[1]
Reserved[0]
LINK[2]
LINK[1]
Bit 8
LINK[0]
Bit 7
Unused
Bit 6
Unused
Bit 5
Unused
Bit 4
R/W
R/W
R/W
R/W
R/W
TSLOT[4]
TSLOT[3]
TSLOT[2]
TSLOT[1]
TSLOT[0]
Bit 3
Bit 2
Bit 1
Bit 0
This register provides the receive link and time-slot number used to access the channel provision
RAM. Writing to this register triggers an indirect register access.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
TSLOT[4:0]:
The indirect time-slot number bits (TSLOT[4:0]) indicate the time-slot to be configured or
interrogated in the indirect access. For a channelised T1 link, time-slots 1 to 24 are valid. For
a channelised E1 link, time-slots 1 to 31 are valid. For unchannelised links, only time-slot 0 is
valid.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
101