RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x040 : GPIC Control
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
X
X
X
0
0
0
0
0
X
X
X
X
0
0
1
0
Unused
R/W
R/W
R/W
R/W
R/W
RPWTH[4]
RPWTH[3]
RPWTH[2]
RPWTH[1]
RPWTH[0]
Unused
Bit 8
Bit 7
Bit 6
Unused
Bit 5
Unused
Bit 4
Unused
Bit 3
R/W
R/W
R/W
R/W
PONS_E
SOE_E
Bit 2
Bit 1
LENDIAN
Reserved
Bit 0
This register configures the operation of the GPIC.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
Reserved:
The Reserved bit must be set low for correct operation of the FREEDM.
LENDIAN:
The Little Endian mode bit (LENDIAN) selects between Big Endian or Little Endian format
when reading packet data from and writing packet data to PCI host memory. When LENDIAN
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
98