RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
Register 0x104 : RCAS Indirect Channel Data
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Unused
Unused
Unused
Unused
Unused
Unused
CDLBEN
PROV
X
X
X
X
X
X
0
0
X
0
0
0
0
0
0
0
R/W
R/W
Bit 8
Bit 7
Unused
CHAN[6]
CHAN[5]
CHAN[4]
CHAN[3]
CHAN[2]
CHAN[1]
CHAN[0]
Bit 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
This register contains the data read from the channel provision RAM after an indirect read
operation or the data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
CHAN[6:0]:
The indirect data bits (CHAN[6:0]) report the channel number read from the channel provision
RAM after an indirect read operation has completed. Channel number to be written to the
channel provision RAM in an indirect write operation must be set up in this register before
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
103