RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
is set low, Big Endian format is selected. When LENDIAN is set high, Little Endian format is
selected. Descriptor references and the contents of descriptors are always transferred in
Little Endian Format. Please refer below for each format's byte ordering.
Table 16 – Big Endian Format
00 Bit 31
24 23
16
15
8
7
Bit 0
BYTE 3
DWORD Address 04
BYTE 0
BYTE 4
BYTE 1
BYTE 5
BYTE 2
BYTE 6
BYTE 7
•
•
•
•
•
•
•
•
•
•
•
•
n-4
BYTE n-4
BYTE n-3
BYTE n-2
BYTE n-1
Table 17 – Little Endian Format
00 Bit 31
DWORD Address 04 BYTE 3
24 23
16
15
8
7
Bit 0
BYTE 2
BYTE 6
BYTE 1
BYTE 5
BYTE 0
BYTE 4
BYTE 7
•
•
•
•
•
•
•
•
•
•
•
•
n-4
BYTE n-1
BYTE n-2
BYTE n-3
BYTE n-4
SOE_E:
The stop on error enable (SOE_E) bit determines the action the PCI controller will take when
a system or parity error occurs. When set high the PCI controller will disconnect the PCI
REQB signal from the PCI bus. This prevents the GPIC from the becoming a master device
on the PCI bus in event of one of the following bits in the PCI Configuration Command/Status
register being set: DPR, RTABT, MABT and SERR. When the SOE_E bit is set low the PCI
controller will continue to allow master transactions on the PCI bus. Setting this bit low after
an error has occurred or clearing the appropriate bit the PCI Configuration Command/Status
register will reactivate the PCI REQB signal and allow the GPIC to resume servicing the local
masters. In the event of a system or parity error it is recommended that the core device be
reset unless the cause of the fault can be determined.
PONS_E:
The Report PERR on SERR enable (PONS_E) bit controls the source of system errors.
When set high all parity errors will be signaled to the host via the SERRB output signal.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PMC [ PMC-SIERRA, INC ]
