RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x000: Master Reset and Identity / Load Performance Meters
Bit
Type
R/W
Function
RESET
TYPE[2]
TYPE[1]
TYPE[0]
ID[3]
ID[2]
ID[1]
ID[0]
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
1
0
0
0
0
1
R
R
R
R
R
R
R
This register allows the revision number of the S/UNI-VORTEX to be read by
software permitting graceful migration to newer, feature-enhanced versions of
the S/UNI-VORTEX.
In addition, writing to this register simultaneously loads all the performance meter
registers in the S/UNI-VORTEX.
ID[3:0]:
The ID bits can be read to provide a binary S/UNI-VORTEX revision number.
TYPE[2:0]:
The TYPE bits can be read to distinguish the S/UNI-VORTEX from the other
members of the S/UNI family of devices.
RESET:
The RESET bit allows the S/UNI-VORTEX to be reset under software control.
If the RESET bit is a logic one, the entire S/UNI-VORTEX is held in reset.
This bit is not self-clearing. Therefore, a logic zero must be written to bring
the S/UNI-VORTEX out of reset. Holding the S/UNI-VORTEX in a reset state
places it into a low power, stand-by mode. A hardware reset clears the
RESET bit, thus negating the software reset. Otherwise, the effect of a
software reset is equivalent to that of a hardware reset with the exception that
the Master Test Register (0x200) is not reset by a software reset. Register
0x200 should be written after a software reset to ensure it is in a known state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
56
PMC [ PMC-SIERRA, INC ]
