RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Register 0x001: Master Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
Reserved
Unused
MINTE
0
X
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
TPAEN
ROUTECC
RX8KSEL[2]
RX8KSEL[1]
RX8KSEL[0]
RX8KSEL[2:0]:
The RX8KSEL select (RX8KSEL[2:0]) bits determine the high-speed serial
link from which RX8K is derived. RX8K is extracted from the RXDn+/- serial
link whose index equals the binary RX8KSEL value.
ROUTECC:
The ROUTECC bit determines how the upstream control channel cells are
handled. If ROUTECC is logic 0, the control channel cells are presented on
the RDAT[15:0] cell bus. If ROUTECC is logic 1, the control channel cells are
directed to the microprocessor port through a four cell FIFO.
TPAEN:
The TPA Enable (TPAEN) bit determines whether the TPA output is driven in
response to polling. If TPAEN is logic 0, TPA is unconditionally high
impedance. If TPAEN is logic 1, TPA drives upon the sampling of a
TADR[11:0] value that lies in the range of addresses specified by the Control
Channel Base Address, Logical Channel Base Address and Logical Channel
Address Range registers. TPAEN should only be set to logic 1 after the
aforementioned registers have been initialized.
MINTE:
The Master Interrupt Enable allows internal interrupt statuses to be
propagated to the interrupt output. If MINTE is logic 1, INTB will be asserted
low upon the assertion of an interrupt status bit whose individual enable is
set. If MINTE is logic 0, INTB is unconditionally high-impedance.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
57
PMC [ PMC-SIERRA, INC ]
