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PM7351-BGI 参数 Datasheet PDF下载

PM7351-BGI图片预览
型号: PM7351-BGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA304, 31 X 31 MM, 1.51 MM HEIGHT, 1.27 MM PITCH, SBGA-304]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 174 页 / 1840 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7351 S/UNI-VORTEX  
DATA SHEET  
PMC-1980582  
ISSUE 5  
OCTAL SERIAL LINK MULTIPLEXER  
Fig. 8 Boundary Scan Architecture  
Boundary Scan  
TDI  
Register  
Device Identification  
Register  
Bypass  
Register  
Instruction  
Register  
and  
Mux  
DFF  
TDO  
Decode  
Control  
TMS  
Test  
Access  
Port  
Select  
Controller  
Tri-state Enable  
TRSTB  
TCK  
The boundary scan architecture consists of a TAP controller, an instruction  
register with instruction decode, a bypass register, a device identification register  
and a boundary scan register. The TAP controller interprets the TMS input and  
generates control signals to load the instruction and data registers. The  
instruction register with instruction decode block is used to select the test to be  
executed and/or the register to be accessed. The bypass register offers a single-  
bit delay from primary input, TDI to primary output, TDO. The device  
identification register contains the device identification code.  
The boundary scan register allows testing of board inter-connectivity. The  
boundary scan register consists of a shift register place in series with device  
inputs and outputs. Using the boundary scan register, all digital inputs can be  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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