RELEASED
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DATA SHEET
PMC-1980582
ISSUE 5
Near end
downstream
Reg 0x0008
Far-end
upstream
Reg 0x00C
LVDS:
both ends
must match
e.g. Reg
0x080 and
0x90
Resultant Cell contents at far-end Bus or Microprocessor
H
5
I
P
R
E
P
E
N
D
H
I
P
U
S
R
H
D
R
P
R
E
P
E
N
D
C
E
L
Note: USRHDR is a two bit value that defines the number of
header bytes transferred over the LVDS link.
00 = 4 bytes
N
A
D
D
U
D
F
5
U
D
F
N
A
D
D
U
D
F
R
E
P
E
N
D
U
D
F
L
01 = 5 bytes (UDF not sent)
C
R
C
10 = 6 bytes (default)
11 = reserved
Note: The LVDS transmitter adds 5 overhead bytes to every
cell, which includes room for PHY address information. Thus
the LVDS cell format is the same whether the PHY address
arrives as a prepend or embedded in the H5/UDF field.
1
1
0
1
1
0
1
4
6
1
0
0
•
59 byte cells (prepend + 4 header bytes, H5&UDF are
removed) are transferred from a 58 byte bus to a 58 byte
bus.
•
•
Prepend and PHY address valid, H5 & UDF exist but are
undefined.
Control cell header bytes 8&9 are undefined at Rx.
Prepend bytes 2&3 are defined.
0
1
X
1
0
0
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
59 byte cells (5 system, 6 header bytes, 48 data bytes)
are transferred from a 58 byte bus to a 54 byte bus.
At receiving bus the H5 & UDF bytes contain the PHY
address. The near-end cell prepend is stripped off and
not sent over the LVDS link. The H5/UDF field is sent to
the far end, but over-written by the PHY address (the
next example shows a similar, but more bandwidth
efficient configuration).
•
•
•
Control cell header bytes 8&9 are valid at far-end
microprocessor. Prepend bytes 2&3 are undefined.
THIS CONFIGURATION NOT VALID IF RANYPHY = 1
57 byte cells (4 header bytes) are transferred from a 58
byte bus to a 54 byte bus.
1
0
1
X
1
0
6
0
0
•
•
At receiving bus the H5 & UDF bytes contain the PHY
address. The near-end cell prepend and H5/UDF is
stripped off and not sent over the LVDS link.
•
•
•
Control cell prepend bytes 2&3 and header bytes 8&9
are undefined at far-end microprocessor.
X
X
1
1
0
0
1
1
0
0
1
1
4
4
0
1
0
1
57 byte cells (4 header bytes) are transferred from a 54
byte bus to a 58 byte bus.
At far-end the prepend, PHY address, and H5/UDF fields
are all present. Word 0 contains the PHY address, but
the prepend and H5/UDF fields are undefined.
Control cell prepend bytes 2&3 and header bytes 8&9
are undefined at far-end microprocessor.
•
•
•
59 byte cells (5 system, 2 CRC, 4 header bytes) are
transferred from a 54 byte bus to a 58 byte bus.
At far-end the prepend, PHY address, and H5/UDF fields
are all present. Word 0 contains the PHY address, the
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
133
PMC [ PMC-SIERRA, INC ]
