RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
downstream Any-PHY bus. If control channel cells are not being inserted
via the Any-PHY bus, care must be taken to set this register to an address
not used by the bus master.
3. TPAEN bit of the Master Configuration register (0x001) – This bit must be
a logic 1 before the TPA output will respond to polling.
Beyond the minimum, the following bits are commonly modified:
1. MINTE bit of the Master Configuration register (0x001) – This bit must be
logic 1 to enable interrupt servicing. If MINTE is logic 0, the INTB output
will be unconditionally high-impedance. Note that individual interrupt
sources must enabled in addition to setting MINTE.
2. ROUTECC bit of the Master Configuration register (0x001) – This bit must
be set to logic 1 if the control channel cells are to be read from the
microprocessor port. If ROUTECC is logic 0, the control channel cells are
routed to the SCI-PHY/Any-PHY upstream bus with a PHY ID of “111110”.
3. ACTIVE bit of the Serial Link Maintenance register (0x095, 0x0B5, 0x0D5,
0x0F5, 0x115, 0x135, 0x145, 0x165) – If this is the active as opposed to
the spare card, this bit must be set to logic 1 to communicate this to the
S/UNI-DUPLEX. Each bit is independent to allow load sharing
configurations.
12.4 JTAG Support
The S/UNI-VORTEX supports the IEEE Boundary Scan Specification as
described in the IEEE 1149.1 standard. The Test Access Port (TAP) consists of
the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP
controller and the boundary scan registers. The TRSTB input is the active-low
reset signal used to reset the TAP controller. TCK is the test clock used to
sample data on input, TDI and to output data on output, TDO. The TMS input is
used to direct the TAP controller through its states. The basic boundary scan
architecture is shown in Fig. 8.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
135
PMC [ PMC-SIERRA, INC ]
