RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x08F, 0x0AF, 0x0CF, 0x0EF, 0x10F, 0x12F, 0x14F, 0x16F:
Downstream Logical Channel FIFO Ready Level
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
X
X
1
1
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
FREADY[5]
FREADY[4]
FREADY[3]
FREADY[2]
FREADY[1]
FREADY[0]
FREADY[5:0]:
The FIFO Ready Level (FREADY[5:0]) register is used to set the earliest time
TPA can be reasserted after a cell has been written into a downstream buffer.
Writing a cell into a downstream buffer causes its TPA value to be
deasserted. After the number of bytes read from the downstream buffer (and
subsequently serialized on TXDn+/-) is greater than or equal to the binary
value of FREADY[5:0], the TPA value returned when that channel is polled
will be logic 1, thus indicating a write to the logical channel can be initiated. If
the buffer is empty when the channel is polled, then FREADY[5:0] is not
relevant since TPA will always be asserted on an empty buffer.
FREADY[5:0] must be set such as to avoid a FIFO overflow. It should always
be less than the cell length (52, 54 or 56 depending on how the Any-PHY bus
is configured). A low value of FREADY[5:0] has the potential to increase the
maximum sustained cell rate for a single logical channel, but it has to be large
enough to ensure the FIFO writes do not catch up to the FIFO reads. The
FREADY[5:0] programming is discussed in the Operations section on Page
127. As a minimum requirement, the programmed value must respect the
following constraint to guarantee no cell loss:
f
REFCLK
FREADY > max(9,56 − 28*
)
f
TCLK
The default value of 50 is compatible with all permissible clock frequency
ranges but it will not be sufficient if a single high speed PHY is all that is
connected to the far-end S/UNI-DUPLEX.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
103
PMC [ PMC-SIERRA, INC ]
