RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x08A, 0x0AA, 0x0CA, 0x0EA, 0x10A, 0x12A, 0x14A, 0x16A:
Logical Channel Base Address
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCBA[10]
LCBA[9]
LCBA[8]
LCBA[7]
LCBA[6]
LCBA[5]
LCBA[4]
LCBA[3]
0
0
0
0
0
0
0
0
LCBA[10:3]
These registers in conjunction with the LCBA[11] bit of the Logical Channel
Range / Logical Channel Base Address MSB registers determine the location
of the logical channels for the serial links within the available address space
for the purposes of polling and transfer selection. This register is only
relevant to the downstream direction; no address remapping is done in the
upstream.
The value of LCBA[11:3]*8 is subtracted from the TADR[11:0] input value
sampled. If the difference is within the range set by the LCAR[1:0] register
bits, TPA will drive the buffer availability status (provided the TPAEN register
bit is logic 1) of the logical channel whose index matches the difference.
The value of LCBA[11:3]*8 is subtracted from the ADDR[11:0] value encoded
in the cell structures (see Fig. 3) received on TDAT[15:0]. If the difference is
within the range set by the LCAR[1:0] register bits, the cell shall be written to
the logical channel buffer whose index matches the difference.
Note that address wraps are supported. For example, if LCBA[11:3] is 0x1FF
and the range is 32 addresses, the addresses from 0xFF8 through 0xFFF
and 0x000 through 0x017 are matched.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PMC [ PMC-SIERRA, INC ]
