RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x08C, 0x0AC, 0x0CC, 0x0EC, 0x10C, 0x12C, 0x14C, 0x16C:
Downstream Logical Channel FIFO Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
Unused
FOVRE
FIFORST
X
X
X
X
X
X
0
R/W
R/W
0
FIFORST:
The FIFORST bit is used to reset all the logical channel FIFOs for a link.
When FIFORST is set to logic 0, the FIFO channels operate normally. When
FIFORST is set to logic 1, all the FIFOs are immediately emptied and ignore
writes. The FIFOs remain empty and continue to ignore writes until logic 0 is
written to FIFORST. This results in a continuous stream of stuff cells on
TXDn+/-.
If a user cell is currently being sent over the LVDS link it will likely be
corrupted by the reset. If the header portion of the cell has been sent then
this corruption will not be detected at the receiver if header error detection is
enabled. However it will likely be detected if cell error detection is enabled.
See Transmit High-Speed Serial Configuration Register, CELLCRC bit, and
Received High-Speed Serial Configuration Register, CELLCRC bit for details.
FOVRE:
The FOVRE bit enables the assertion of the INTB output due to a FIFO
overrun error condition. When FOVRE and the Master Interrupt Enable bit of
the Master Configuration register are set to logic 1, the interrupt is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
101
PMC [ PMC-SIERRA, INC ]
