RELEASED
PM7351 S/UNI-VORTEX
DATA SHEET
PMC-1980582
ISSUE 5
OCTAL SERIAL LINK MULTIPLEXER
Registers 0x091, 0x0B1, 0x0D1, 0x0F1, 0x111, 0x131, 0x151, 0x171:
Transmit High-Speed Serial Cell Count Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R
R
XFERE
XFERI
OVR
Unused
Unused
Unused
Unused
Unused
0
X
X
X
X
X
X
X
This register indicates whether the associated Transmit Cell Count registers have
been updated with new data and whether this data overwrites unacknowledged
data. This status is maintained on a per-serial link basis.
OVR:
The OVR bit is the overrun status of the associated Transmit Cell Count
registers. A logic 1 in this bit position indicates that a previous transfer
(indicated by XFERI being logic 1) has not been acknowledged before the
next accumulation interval has occurred and thus the contents of the Transmit
Cell Count registers have been overwritten. OVR is set to logic 0 when this
register is read.
XFERI:
The XFERI bit indicates that a transfer of Transmit Cell Count data has
occurred. A logic 1 in this bit position indicates that the associated Transmit
Cell Count registers have been updated. This update is initiated by writing to
one of the associated Transmit Cell Count register locations or by writing to
the Load Performance Meters (0x000) register. XFERI is set to logic 0 when
this register is read.
XFERE:
The XFERE bit enables the generation of an interrupt when an accumulation
interval is completed and new values are stored in the associated Transmit
Cell Count registers. When XFERE and the Master Interrupt Enable bit of the
Master Configuration register are set to logic 1, the INTB output is asserted
low if the XFERI bit is a logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
106
PMC [ PMC-SIERRA, INC ]
