RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Registers 0x18, 0x1A:
RXD1, RXD2 Bit Oriented Code Receiver Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
Unused
Unused
IDLE
X
X
X
X
X
0
R/W
R/W
R/W
AVC
BOCE
0
0
These registers select the validation criteria to be used in determining a valid bit
oriented code (BOC) and enables generation of an interrupt on a change in code
status of the BOC received on RXD1+/- and RXD2+/-.
IDLE:
The IDLE bit enables the assertion of the INTB output when there is a
transition from a validated BOC to idle code. When IDLE and the Master
Interrupt Enable bit of the Master Configuration register are set to logic 1, the
interrupt is enabled.
AVC:
The AVC bit position selects the validation criteria used in determining a valid
BOC. A logic 1 in the AVC bit position selects an alternate validation criterion
of 4 out of 5 matching BOCs; a logic 0 selects the 8 out of 10 matching BOC
criterion. Unless fast declaration is necessary, it is recommended that AVC be
set to logic 0 to improve bit error tolerance.
BOCE:
The BOCE bit enables the assertion of the INTB output when a valid BOC is
detected. When BOCE and the Master Interrupt Enable bit of the Master
Configuration register are set to logic 1, the interrupt is enabled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
116
PMC [ PMC-SIERRA, INC ]
