RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x20: Microprocessor Cell Buffer Interrupt
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
EXTCRCERRI
EXTRDYI
X
X
X
X
0
0
0
0
INSOVRI
INSRDYI
EXTCRCERRE
EXTRDYE
INSOVRE
R
R/W
R/W
R/W
R/W
INSRDYE
The Master Interrupt Enable bit of the Master Configuration register must also be
logic 1 for the interrupt enables to take effect.
INSRDYE:
The INSRDYE bit allows the generation of an interrupt signal when the Insert
FIFO becomes available. When INSRDYE is set to logic 1, the INTB output is
asserted low when the INSRDYI bit is logic 1.
INSOVRE:
The INSOVRE bit controls the generation an interrupt signal when a write
access is done to a full Insert FIFO. When INSOVRE is set to logic 1, the
INTB output is asserted low when the INSOVRI bit is logic 1.
EXTRDYE:
The EXTRDYE bit allows the generation of an interrupt signal when an
Extract FIFO becomes ready. When EXTRDYE is set to logic 1, the INTB
output is asserted low when the EXTRDYI bit is logic 1.
EXTCRCERRE:
The EXTCRCERRE bit controls the generation an interrupt signal upon
detection of a CRC-32 error at the end of a cell read access. When
EXCRCERRE is set to logic 1, the INTB output is asserted low when the
EXTCRCERRI bit is logic 1.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
119
PMC [ PMC-SIERRA, INC ]
