RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
INSRDYI:
The INSRDYI bit provides the status of the Insert FIFO Ready Interrupt. This
bit is set to logic 1 when the Insert FIFO becomes ready to accept a cell (i.e.
a cell is transferred from a full FIFO) or upon the completion of a cell write if
at least one more cell can be written. Ready status of a specific FIFO is
indicated by a logic 1 at the corresponding bit of the Microprocessor Insert
FIFO Ready register. The INSRDYI bit is reset immediately after a read to this
register.
INSOVRI:
The INSOVRI bit indicates the status of the write access to the Insert FIFO.
This bit is set to high when a write access has being done to a full Insert FIFO
and that the data has been discarded. This bit is reset immediately after a
read to this register.
EXTRDYI:
The EXTRDYI bit provides the status of the Extract FIFOs Ready Interrupt.
This bit is set to logic 1 when one of the Extract FIFO becomes ready for a
cell read (i.e. upon reception of the only cell in the FIFO) or upon the
completion of a cell read if there is at least one more cell to be read from the
FIFO. Ready status of a specific FIFO is indicated by a logic 1 at the
corresponding bit of the Microprocessor Insert FIFO Ready register. This bit is
reset immediately after a read to this register.
EXTCRCERRI:
The EXTCRCERRI bit indicates the CRC-32 status of a cell read from an
Extract FIFO. When the EXTCRCCHK bit is set to logic 1, the EXTCRCERRI
bit is updated when the last byte of a cell is read by the microprocessor. It is
set to logic 1 if the value of the Extract CRC Accumulator register differs from
the expected CRC-32 remainder polynomial. Otherwise, it is set to logic 0.
This bit is also reset immediately after a read to this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
120
PMC [ PMC-SIERRA, INC ]
