RELEASED
PM7350 S/UNI-DUPLEX
DATA SHEET
PMC-1980581
ISSUE 5
DUAL SERIAL LINK PHY MULTIPLEXER
to logic 1 (default) and the eight bit SCI-PHY/Any-PHY cell format is used
(OBUS8 input set to logic 1), the H5 byte is included, i.e. the optional “Word
7” illustrated in Fig. 6, in the data structure expected on ODAT[7:0]. When
H5UDF is set to logic 1 (default) and the 16 bit SCI-PHY/Utopia/Any-PHY cell
format is used (OBUS8 input set to logic 0), the H5 and UDF octets are
included, i.e. the optional “Word 4” illustrated in Fig. 7, in the data structure
expected on ODAT[15:0].
INADDUDF:
The INADDUDF bit relocates the word identifying the logical channel in the
H5/UDF field when the output port is configured as a SCI-PHY/Utopia bus
slave. When this bit is set to logic 1 and eight bit cell format is used (OBUS8
input set to logic 1), the logical channel is identified in the five lower bits of the
H5 byte. The three upper bits of the H5 register are set to the value of the
three least significant bits of the Extended Address Match register, which
default to all zeros. When this bit is set to logic 1 and 16 bit cell format is
used (OBUS8 input set to logic 0), the logical channel is identified in the five
lower bits of the H5/UDF word. The eleven remainder bits of the H5/UDF
word are set to the value of the Extended Address Match register, which
default to all zeros. In both cases, “Word 0” is excluded from the cell data
(refer to Fig. 6 and Fig. 7).
For proper operation to occur when INADDUDF is set to 1 the H5UDF bit
must also be set to one (its default value). This bit has no effect when the
SCI-PHY/Any-PHY Output port is not configured as a SCI-PHY/Utopia bus
slave.
CELLXFERRE:
The Cell Transfer Error Interrupt Enable (CELLXFERRE) bit allows the
generation of an interrupt on an invalid selection by an external master
device. This occurs when a cell transfer is attempted, but the S/UNI-DUPLEX
has indicated no cell is available by returning OCA low when polled. When
CELLXFERRE is set to logic 1, the INTB output is asserted low when the
CELLXFERRI bit is logic 1.
CELLXFERRI:
The CELLXFERRI bit provides a status of the Cell Transfer Error Interrupt.
The CELLXFERRI is only valid when the SCI-PHY/Any-PHY Interface output
port is configured as a bus slave (OMASTER=low). This interrupt status is
asserted upon the selection by the external bus master of the SCI-PHY/Any-
PHY Interface output port for a transfer without a cell being available, i.e. the
S/UNI-DUPLEX has indicated no cell is available by returning OCA low when
polled. The CELLXFERRI bit will not be asserted when the OENB is
maintained low beyong the end of a cell transfer even if no new cell is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
113
PMC [ PMC-SIERRA, INC ]
