RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Table 10 SCI-PHY/Utopia and Any-PHY Comparison, Ingress Direction
Attribute
Latency
SCI-PHY
Any-PHY
ICA is driven high or low immediately ICA is driven or becomes high
upon sampling IAVALID high and
becomes high impedance
impedance on the IFCLK rising edge
following the one that samples a
immediately upon sampling IAVALID IAVALID low or high respectively.
low.
Logical
Channel
Selection
Logical channel is selected by
IADDR[4:0] when IENB was last
sampled high.
An extra word (Word 0) is prepended
to the cell coincident with the assertion
of the ISX signal. Word 0 is used for
logical channel selection
ISX
Unused.
High coincident with the first word of
the cell data structure.
ISOC
High coincident with the first word of
the cell data structure.
Unused in the S/UNI-DUPLEX.
Autonomous
deselection
Not supported. A subsequent cell is
input (provided space is available) if
Supported. Subsequent writes are
ignored if IENB is held low until ISX
IENB is held low beyond the end of a input is asserted.
cell.
The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell
format of the input bus. An Any-PHY input bus slave requires the embedded
PHY ID to be present in Byte 0 or Word 0. The cell format options for the 8 bit
bus (shown in Fig. 6) are described in Table 11. 16 bit bus options (shown in Fig.
7) are described in Table 12.
Table 11 Eight Bit Any-PHY Bus Slave, Input Configuration
Byte
Register 0x0C
H5UDF PRELEN
Notes
#
bytes
53
54
54
55
55
55
0
1
2
7
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
N
N
N
Y
Y
N
Y
N
Y
N
Y
0
1
0
1
0
1
00
00
01
01
10
10
PHY ID byte, then H1-H4, no H5 byte
Default setting. PHY ID, then H1-H5
PHY ID, 1 user byte then H1-H4
PHY ID, 1 user byte then H1-H5
PHY ID, 2 user bytes then H1-H4
PHY ID, 2 user bytes then H1-H5
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
55
PMC [ PMC-SIERRA, INC ]
