RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 7 Sixteen Bit SCI-PHY/Utopia/Utopia Cell Format
Bit 15
Bit 4
Bit 0
Bit 5
Extended
Address
W ord 0
(optional)
PHYID[4:0]
W ord 1
(optional)
User Prepend
H1
H3
H2
W ord 2
H4
W ord 3
W ord 4
(optional)
1
1
UDF
H5
PAYLOAD1
PAYLOAD3
PAYLOAD2
PAYLOAD4
W ord 5
W ord 6
W ord 28
PAYLOAD47
PAYLOAD48
Note 1: Optionally, the H5/UDF fields can be overwritten by the
Extended Address and PHYID[4:0].
9.2 Clocked Serial Data Interface
In some systems the PHY devices to which the S/UNI-DUPLEX is to interface
may not contain an integrated Transmission Convergence function even though
the low level protocol being transported over that interface is I.432 compliant ATM
cells. For these types of devices (typically framers or modems) the S/UNI-
DUPLEX provides up to 16 bi-directional clocked serial data interfaces with fully
integrated, I.432 compliant, Transmission Convergence (TC) functions to allow
cell structured bit streams to be exchanged with the modems. The modems
perform all Physical Media Dependent (PMD) functions so that the bit streams
contain only contiguous ATM cells. The S/UNI-DUPLEX requires that the clock is
gapped during PMD overhead bit locations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
59
PMC [ PMC-SIERRA, INC ]
