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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
The SCI-PHY/Any-PHY Input Configuration 1 register (0x0C) determines the cell  
format of the input bus. A SCI-PHY/Utopia input bus slave neither requires nor  
supports embedded PHY ID. The cell length options for the 8 bit bus (shown in  
Fig. 6) are described in Table 6. 16 bit bus options (shown in Fig. 7) are  
described in Table 7. Note that these options are identical to the SCI-PHY/Utopia  
input bus master configuration.  
Table 6 Eight Bit SCI-PHY/Utopia Bus Slave, Input Configuration  
Byte  
Register 0x0C  
H5UDF PRELEN  
Notes  
H1-H4, no H5 byte  
#
bytes  
52  
53  
53  
54  
54  
55  
0
1
2
7
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
Y
Y
N
Y
N
Y
N
Y
0
1
0
1
0
1
00  
00  
01  
01  
10  
10  
Default, Utopia compatible  
1 user byte then H1-H4  
1 user byte then H1-H5  
2 user bytes then H1-H4  
2 user bytes then H1-H5  
Table 7 Sixteen Bit SCI-PHY/Utopia Bus Slave, Input Configuration  
Word  
Register 0x0C  
H5UDF PRELEN  
Notes  
H1-H4, no H5/UDF field  
#
bytes  
52  
54  
54  
0
1
4
N
N
N
N
N
N
Y
Y
N
Y
N
Y
0
1
0
1
00  
00  
01  
01  
Default, Utopia compatible  
1 user word then H1-H4  
56  
1 user word, H1-H4, then H5/UDF  
In the egress direction (cells are transferred from the LVDS to the output port),  
the port appears as a single addressable SCI-PHY/Utopia Level 2 slave. The  
cells received on the high-speed serial link are queued in FIFOs dedicated to  
each logical channel. The corresponding PHY ID of each cell is encoded in  
system prepend bytes sent over the LVDS link. The S/UNI-DUPLEX  
autonomously multiplexes the traffic from up to 32 logical channels and presents  
it as a single cell stream on the output bus. If at least one cell is present in any of  
the FIFOs, OCA will drive high when the device is polled.  
Polling occurs when OAVALID is sampled high and the sampled OADDR[4:0]  
matches the OAD[4:0] bits in the Output Address Match register. Utopia L2  
compatibility is achieved if OAVALID is tied high and OAD[4:0] is not all ones.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
52  
 
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