欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7350-PGI的Datasheet PDF文件第65页浏览型号PM7350-PGI的Datasheet PDF文件第66页浏览型号PM7350-PGI的Datasheet PDF文件第67页浏览型号PM7350-PGI的Datasheet PDF文件第68页浏览型号PM7350-PGI的Datasheet PDF文件第70页浏览型号PM7350-PGI的Datasheet PDF文件第71页浏览型号PM7350-PGI的Datasheet PDF文件第72页浏览型号PM7350-PGI的Datasheet PDF文件第73页  
RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Table 9 Sixteen Bit SCI-PHY/Utopia Bus Slave, Output Configuration  
Word  
Register 0x14  
INADD  
UDF  
H5  
UDF  
PRE  
LEN  
Notes  
#
bytes  
54  
0
1
4
Y
Y
N
N
N
Y
0
0
0
1
00  
00  
PHY ID in Word 0, H1-H4 only  
Default, PHY ID in Word 0, H1-H4,  
H5/UDF  
56  
56  
58  
Y
Y
Y
Y
N
Y
0
0
0
1
01  
01  
PHY ID in Word 0, 2 user bytes, H1-H4  
PHY ID in Word 0, 2 user bytes, H1-H4,  
H5/UDF  
Most common setting when Utopia  
compatibility is desired. Standard 54  
byte cell, PHY ID embedded in H5/UDF.  
2 user bytes, H1-H4, PHY ID in H5/UDF  
54  
N
N
Y
1
X
00  
56  
N
Y
Y
1
X
01  
9.1.3 Any-PHY Slave  
The Any-PHY bus slave format is enabled when the IANYPHY and OANYPHY  
inputs are high, and IMASTER, and OMASTER inputs are all tied low.  
In the ingress direction (cells are transferred from the parallel bus input port to  
the LVDS links), the port presents itself as 32 PHY entities. Cells read from the  
bus are queued in a dedicated FIFO for each logical channel. As in the SCI-PHY  
bus mode, the ability of the FIFOs to accept additional cells is discovered through  
polling using the IADDR[4:0] and IAVALID inputs. Upon IAVALID being sampled  
low (note this is opposite to SCI-PHY mode) the ICA output is asserted if the cell  
FIFO for the logical channel addressed by IADDR[4:0] has at least one empty  
cell buffer. If the FIFO is full, ICA is deasserted. If a cell transfer is in progress  
that will fill a logical channel FIFO, ICA will also be deasserted. If IAVALID is  
sampled high ICA becomes high impedance. ICA is delayed by one bus cycle  
(i.e. one IFCLK cycle) in the Any-PHY bus configuration.  
In Any-PHY mode cell transfer is initiated using inband selection. The first word  
of the cell, coincident with the assertion of the ISX signal, is used for logical  
channel selection. Cells are accepted by the S/UNI-DUPLEX if the value in the  
Extended Address field of Word 0 agrees with the Extended Address Match  
registers over the range of bits specified by the Extended Address Mask  
registers.  
Table 10 summarizes the distinctions between the SCI-PHY/Utopia and Any-PHY  
protocols in the ingress direction.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
54  
 
 复制成功!