RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
IDAT[15]
IDAT[14]
IDAT[13]
IDAT[12]
IDAT[11]
IDAT[10]
IDAT[9]
IDAT[8]
IDAT[7]
IDAT[6]
IDAT[5]
IDAT[4]
IDAT[3]
IDAT[2]
IDAT[1]
IDAT[0]
Input
B1 The Input Data bus (IDAT[15:0]) carries the ATM
C2 cell words that are written to the upstream cell
C1 buffer. Only IDAT[7:0] are used if the IBUS8 input is
D2 high.
(SCIANY
= 1)
D3
D1
E1
E3
E4
F2
IDAT[15:0] is sampled on the rising edge of IFCLK.
As a SCI-PHY/Utopia bus master (IMASTER=1,
IANYPHY=0) the IDAT[15:0] bus is considered valid
only when the IENB signal was low in the previous
cycle.
As a bus slave (IMASTER = 0) the IDAT[15:0] bus
is considered valid when the IENB signal is
asserted low or the ISX signal is asserted high. As
an Any-PHY bus slave (IMASTER = 0,
IANYPHY=1) IDAT[15:0] bus is not considered valid
when autonomous deselection occurs after the last
word of a cell.
F1
G1
G4
H3
G3
H1
These inputs are only active if the SCIANY input is
a logic high.
IPRTY
Input
B2 The Input Parity (IPRTY) signal completes the parity
(programmable for odd or even parity) of the
IDAT[15:0] bus when IBUS8 is low and the
IDAT[7:0] bus when IBUS8 is high. A maskable
interrupt and a status bit are generated upon a
parity error; no other actions are taken.
The IPRTY signal is sampled on the rising edge of
IFCLK. As a SCI-PHY/Utopia bus master
(IMASTER=1, IANYPHY=0) IPRTY is considered
valid only when the IENB signal was low in the
previous cycle.
As a bus slave (IMASTER=0) IPRTY is considered
valid coincident with IENB being asserted low or
ISX being asserted high. As an Any-PHY bus slave
(IMASTER = 0, IANYPHY = 1) IPRTY is not
considered valid when autonomous deselection
occurs after the last word of a cell.
This input is only active if the SCIANY input is a
logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
24
PMC [ PMC-SIERRA, INC ]
