RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
SCIANY
Input
C7 The SCI-PHY/Any-PHY Interface (SCIANY) input
selects the type of PHY device interface. If SCIANY
is a logic high, the S/UNI-DUPLEX will be
configured to communicate to the PHY devices via
a shared SCI-PHY Level 2, Utopia L2, or Any-PHY
cell bus. If SCIANY is a logic low, each PHY device
has a dedicated clocked bit serial interface.
The two types of interfaces share common package
pins. Failure to present the correct logic level on
this signal for the application may result in damage
to the S/UNI-DUPLEX or the PHY devices.
When SCIANY is logic high, LTXD[3] and LTXD[0]
become inputs and need to be tied to VDD or VSS
through a pull up or a pull down.
LRXD[15]
LRXD[14]
LRXD[13]
LRXD[12]
LRXD[11]
LRXD[10]
LRXD[9]
LRXD[8]
LRXD[7]
LRXD[6]
LRXD[5]
LRXD[4]
LRXD[3]
LRXD[2]
LRXD[1]
LRXD[0]
Input
D6 The low-speed receive data (LRXD[15:0]) inputs
A4 provide data from individual modem channels. The
B4 data streams must carry contiguous ATM cells with
D2 valid HCS (Header Check Sequence) bytes.
(SCIANY=
0)
E3
J2
K3
L2
P2
M4
N6
L6
LRXD[n] can be clocked either by the rising or
falling edge of the corresponding LRXC[n] input,
depending on the value of the LRXCINV bit of the
Master Configuration register. By default, the rising
edge is used.
These inputs are only active if the SCIANY input is
a logic low.
L7
P9
M9
L10
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
19
PMC [ PMC-SIERRA, INC ]
