RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
• Dual 4-wire LVDS serial transceivers each operating at 100 to 200 Mbps
across PCB or backplane traces, or across up to 10 meters of 4-wire
twisted pair cabling for inter-shelf communications.
• Full integrated LVDS clock synthesis and recovery. No external analog
components are required.
• Usable bandwidth (excludes system overhead) of 186 Mbps.
LVDS TRANSMIT DIRECTION
• Simple round robin multiplex of up to 32 PHYs (or 16 clock and data
interfaces) plus the microprocessor port’s cell transfer buffer.
• Multiplexed cell stream broadcast to both LVDS simultaneously.
• 6 bit port ID prepended to each cell for use by ATM layer to identify cell
source (1 of 32 PHYs or processor).
• Back-pressure provided by far end (active link only) to prevent overflow of
far end receiver.
LVDS RECEIVE DIRECTION
• Cells received from the active LVDS link are forwarded to the appropriate
PHY, bit serial interface, or the microprocessor port as specified by a 6 bit
port ID added to each cell at the far end device.
• The LVDS link marked as "spare" is monitored for errors, PHY cells are
discarded, microprocessor port cells are accepted.
• Individual PHY and microprocessor FIFO back-pressure indications are
sent to the far end to prevent FIFO overflows. Per stream back-pressure
prevents head-of-line blocking.
MICROPROCESSOR INTERFACE
• 8 bit data bus, 8 bit address bus.
• Provides read/write access to all configuration and status registers.
• Provides CRC32 calculation and cell transfer registers to support an
embedded microprocessor to microprocessor communication channel
over the LVDS link.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
