RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
IMASTER
Input
A6 The input port master select (IMASTER) pin
determines the direction of the input port cell
interface control signals.
If IMASTER is low, the input port of the S/UNI-
DUPLEX is a bus slave and complies with the SCI-
PHY/Utopia or Any-PHY transmit protocol
depending of the state of the IANYPHY input. The
IADDR[4:0], IAVALID, IENB signals are inputs. The
ICA signal is an output.
If IMASTER is high, the input port of the S/UNI-
DUPLEX is a bus master and complies with the
SCI-PHY/Utopia receive protocol (IANYPHY must
be set to low if IMASTER is high). The IADDR[4:0],
IAVALID, IENB signals are outputs. The ICA signal
is an input.
This input is only active if the SCIANY input is a
logic high.
IBUS8
IFCLK
Input
Input
C6 The input port bus width select (IBUS8) selects the
interface bus width. When IBUS8 is high, only
IDAT[7:0] are expected to present valid data and
IDAT[15:8] are ignored. When IBUS8 is low, all
IDAT[15:0] inputs are used.
This input is only active if the SCIANY input is a
logic high.
F4 The input FIFO clock (IFCLK) is used to read words
into the S/UNI-DUPLEX upstream cell buffer.
IFCLK must cycle at a 52 MHz or lower
instantaneous rate. All SCI-PHY/Any-PHY input
port timing is relative to the rising edge of IFCLK.
This input is only active if the SCIANY input is a
logic high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
22
PMC [ PMC-SIERRA, INC ]
