RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Ball
Name
Ball
No. Function
Type
High Speed LVDS Links
LTXC[15]
LTXC[14]
LTXC[13]
LTXC[12]
LTXC[11]
LTXC[10]
LTXC[9]
LTXC[8]
LTXC[7]
LTXC[6]
LTXC[5]
LTXC[4]
LTXC[3]
LTXC[2]
LTXC[1]
LTXC[0]
Input
B6 The low-speed transmit clock (LTXC[15:0]) inputs
D5 provide timing for the transmit links. Each LTXC
B1 signal is independent of the others.
(SCIANY
= 0)
C1
E1
F1
F4
H3
H1
H4
L3
Each signal in LTXD[15:0] is updated either on the
rising or the falling edge of the corresponding
LTXC[15:0] clock, depending on the value of the
LTXCINV bit of the Master Configuration register.
By default, the rising edge is used.
As an option, clock gaps can be recognized to
force byte alignment to the transmission overhead.
M3
N2
P7
M10
N10
These outputs are only active if the SCIANY input is
a logic low.
Maximum clock rate is 50 MHz.
Input Parallel Bus – (SCIANY is logic high)
IANYPHY
Input J1 The Input Port Any-PHY configuration (IANYPHY)
input determines the protocol of the SCI-PHY/Any-
PHY input port interface. IANYPHY is only active if
the SCIANY input is a logic high.
If IANYPHY is logic low, the interface complies to
the SCI-PHY/Utopia specification.
If IANYPHY is logic high, the interface complies to
the Any-PHY specification. The Any-PHY protocol
is supported only when the input port cell interface
is configured as a bus slave (IMASTER input must
be set to logic 0 if IANYPHY is high).
IANYPHY is an asynchronous input and is expected
to be held static.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PMC [ PMC-SIERRA, INC ]
