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PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
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RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Far-End  
Near-End  
Resultant Cell contents at far-end Bus or Microprocessor  
input  
Reg  
output  
Reg 0x14  
LVDS: both ends must match e.g. Reg 0x40, 0x50 and 0x60  
0x0C  
S
C
I
A
N
Y
H
5
U
D
F
P
S
C
I
A
N
Y
H
5
U
D
F
I
P
R
E
L
E
N
[1  
..  
DEFAULT CONFIGURATION  
5 system, 2 prepend, 4 header and 48 data bytes  
R
E
L
E
N
[1  
..  
N
A
D
D
U
D
F
USRHDR:  
PREPEND:  
CELLCRC:  
4
1
1
Control cell prepend byte 2 is carried as is, but prepend  
byte 3 is overwritten with the CRC8. Header bytes 8&9  
are undefined.  
0]  
0]  
1
1
1
0
1
1
1
1
0
1
Cells are transferred from a 53/53/54(54/54/56) byte bus  
to a 54/55/55(56/58/58) byte bus.  
At far-end the prepend and H5/UDF fields are all  
present. The first byte the prepend is undefined, the  
second byte contains the CRC8 from the previous cell.  
H5 (H5/UDF) is undefined.  
Cells are transferred from the CSD receive port to a  
54/55/55(56/58/58) byte bus.  
At far-end the prepend and H5/UDF fields are all  
present. The first byte the prepend is undefined, the  
second byte contains the CRC8 from the previous cell.  
H5 (H5/UDF) is undefined  
X
X
0
1
1
1
1
1
1
0
0
1
X
X
X
1
X
1
Cells are transferred from a 54/54/55(56/56/58) byte bus  
to the CSD transmit port.  
THIS CONFIGURATION IS VALID ONLY IF OMASTER=0  
AND OANYPHY=0 AT THE FAR-END.  
Cells are transferred from a 53/53/54(54/54/56) byte bus  
to a XX/54/XX(XX/56/XX) byte bus (SCI-ANY slave  
only).  
At far-end the prepend(s) and H5(H5/UDF) fields are all  
present. The first byte the prepend is undefined, the  
second byte (OBUS8=0) contains the CRC8 from the  
previous cell.  
At far-end the H5 (H5/UDF) field contains the PHY  
address.  
12.3 Maximum Cell Bit Rate  
The maximum cell bit rate transferred over the LVDS link is a function the LVDS  
bit rate and the ratio of transport overhead (system prepend & unused user  
defined field) versus cell data. Since the system prepend is fixed at 5 bytes, the  
absolute maximum throughput is achieved when the cell length is 56 bytes, i.e.  
the transported cells included 2 prepend bytes, H5 and UDF.  
Ratiomax = 56/61 = 91.8%, CellBRmax = 91.8% * 200 = 183.6 Mb/s  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
195  
 
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