RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
In the downstream direction the equipment must handle a similar issue, the “big
pipe feeding little pipe” problem. When a large burst of traffic destined for a
single line port is received at the high speed WAN port it must be buffered and
managed as it queues up waiting for the much lower speed line port to clear.
The line cards are always the most numerous cards in this type of equipment.
An individual line card, even if it terminates a few dozen low speed ports, does
not generate or receive enough traffic to justify putting complex buffering and
traffic management devices on it. The ideal architecture has low cost “dumb” line
cards and a feature rich, “smart” core card. In order to enhance fault tolerance,
the architecture should also inherently support 1:1 protection using a redundant
core card and WAN up-link without significantly increasing line card complexity.
A system architecture that keeps buffering and traffic management off the line
card with typically exhibit the following features:
1. Connection setup is simpler both in terms of programming and during
execution because there is minimal or no requirement for line
intervention during the connection setup process.
2. In-service feature upgrades are simpler because feature complexity is
limited to the common equipment.
3. Component costs are reduced, while system reliability increases due to
reduced component count.
In this type of architecture there are often three stages of signal concentration or
multiplexing, as shown in Fig 2.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
6
PMC [ PMC-SIERRA, INC ]
