RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
• In the LVDS receive direction: selects traffic from the LVDS link marked active
and demultiplexes the individual cell streams to the appropriate PHY device.
• Cell read/write to both LVDS links available through the processor port.
Provides optional hardware assisted CRC32 calculation across cells to
support an embedded inter-processor communication channel across the
LVDS links.
• Requires no external memories.
• Standard 5 pin P1149.1 JTAG test port.
• Low-power, 3.3V CMOS technology.
• 160-pin high-performance plastic ball grid array (PBGA) package.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
2
PMC [ PMC-SIERRA, INC ]
