RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Fig. 2 Three Stage Multiplex Architecture
Line Card #1
Modem
S/UNI-
DUPLEX
Modem
Modem
Line Card #2
Modem
Modem
Modem
S/UNI-
VORTEX
S/UNI-
DUPLEX
Policing
OA&M
Buffering
Discard
Scheduling
WAN
S/UNI-
OA&M
up-link
VORTEX
WAN Card
Line Card #N
Modem
Modem
Modem
S/UNI-
DUPLEX
The first stage resides on the line card and spans only those ports physically
terminated by that card. Since it is confined to a single card, this first stage of
multiplexing readily lends itself to the simple parallel bus based multiplex
topology implemented by the S/UNI-DUPLEX. The second stage of
concentration occurs between the core card(s) and the line cards, including line
cards that are on a separate shelf. This second stage is best served by a
redundant serial point-to-point technology. The third stage of multiplexing is
optional and resides on the core card. This third stage is used in systems with a
large number of line cards that require several devices to terminate the second
stage of aggregation. Since the third stage of aggregation is confined to the core
card, it lends itself readily to a parallel bus implementation. This three stage
approach is implemented directly by the S/UNI-DUPLEX and its sister device, the
S/UNI-VORTEX.
The S/UNI-DUPLEX acts as the line card’s bus master. It implements the first
stage of multiplexing by routing traffic from the PHYs and transmitting the traffic
simultaneously over two high speed (200 Mbps) serial 4-wire LVDS links. One
serial link attaches to the active core card, the other to the standby core card. In
the downstream direction the S/UNI-DUPLEX demultiplexes traffic from the
active core card’s LVDS serial link and routes this traffic to the appropriate PHYs.
If the active core card (or its LVDS link) should fail, protection switching
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
7
PMC [ PMC-SIERRA, INC ]
