RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
commands embedded in the spare LVDS link will direct the S/UNI-DUPLEX to
start receiving its traffic from this spare link.
The S/UNI-VORTEX resides on the core card and terminates up to 8 LVDS links
connected to 8 S/UNI-DUPLEX devices. The S/UNI-VORTEX implements the
second stage of multiplexing. More than one S/UNI-VORTEX will be required if
more than 8 links are required – as will be the case for a system with more than 8
line cards. The S/UNI-VORTEX device(s) share a high speed parallel bus with
the core card’s traffic management and OA&M layers, as implemented by
devices such as PMC-Sierra’s S/UNI-APEX and the S/UNI-ATLAS.
Some applications use framer or modem devices without integrated I.432
processing1 normally support a clock and data interface, and rely on external
circuitry to detect and generate ATM cell framing and overhead. To support these
applications, the S/UNI-DUPLEX provides a clock and data mode2. In this mode,
the input/output pins that normally interface to the Utopia bus are configured to
support up to 16 clock and data serial interfaces. This type of line card is shown
in Fig. 3. The I.432 processing is transparent to the far end device, which implies
that a single S/UNI-VORTEX can simultaneously interface to line cards that
implement the Utopia bus and to line cards that use clock and data interfaces.
Fig. 3 Clock and Data PHY Interface
Line Card
Rx Clock
Rx Data
Modem #1
Tx Clock
S/UNI-
DUPLEX
4-wire
Tx Data
LVDS
Modem #16
1 Cell delineation, payload scrambling-descrambling, idle cell generation/discard, etc..
2 Either Utopia mode or clock and data mode can be selected, but not both at once.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
8
PMC [ PMC-SIERRA, INC ]
