RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Some PHY devices provide a 3-line interface consisting of clock, data, and
overhead indication. For these PHYs external circuitry can be used to adapt to
the S/UNI-DUPLEX’s 2-line interface.
In the clock and data receive direction the S/UNI-DUPLEX performs bit level ATM
cell delineation function. In the transmit direction the S/UNI-DUPLEX can
operate in either bit or frame aligned mode. In frame mode (also called byte
aligned mode) the two wire transmit interface continuously monitors for gaps in
the transmit clock to determine where the frame or byte alignment should occur.
The circuitry assumes that when a gap in the transmit clock is detected this is
either the framing bit position (e.g. the DS-1 framing bit) or an overhead byte
(e.g. ADSL modem). In either case the next clock period after the gap is
assumed to represent the byte alignment position.
In the multiplexer application discussed previously the S/UNI-DUPLEX’s LVDS
interfaces are connected to one or two S/UNI-VORTEX devices. It is also
possible to interface S/UNI-DUPLEX to S/UNI-DUPLEX via the LVDS link. Since
the S/UNI-DUPLEX bus interface can be configured in several ways (clock and
data, 8/16 bits bus master, 8/16 bit bus slave) there are various applications
where two S/UNI-DUPLEX devices can be used “back-to-back” in order to
perform one or more of the following functions:
1. Interfacing a bus master device to another bus master.
2. Interfacing a bus slave device to another bus slave.
3. Converting between 8 bit and 16 bit buses.
4. Off card or off shelf bus extension.
5. Cell delineation (I.432 processing).
6. Protection switching.
Examples of these types of configurations are shown in Fig. 4 and Fig. 5.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
9
PMC [ PMC-SIERRA, INC ]
