RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
11.2 JTAG Test Port
The S/UNI-DUPLEX JTAG Test Access Port (TAP) allows access to the TAP
controller and the 4 TAP registers: instruction, bypass, device identification and
boundary scan. Using the TAP, device input logic levels can be read, device
outputs can be forced, the device can be identified and the device scan path can
be bypassed. For more details on the JTAG port, please refer to the Operations
section.
Instruction Register
Length - 3 bits
Instructions
Selected
Register
Instruction
Codes, IR[2:0]
EXTEST
IDCODE
SAMPLE
BYPASS
BYPASS
STCTEST
BYPASS
BYPASS
Boundary Scan
Identification
Boundary Scan
Bypass
Bypass
Boundary Scan
Bypass
000
001
010
011
100
101
110
111
Bypass
Identification Register
Length - 32 bits
Version number - 1H
Part Number - 7350H
Manufacturer's identification code - 0CDH
Device identification - 173500CDH (with CDSDIS tied to VSS).
Length - 100 bits
Table 18: Boundary Scan Register
Pin/Enable Register Cell
Enable Pin/Enable
Register Cell
Enable
Bit
Type
Bit
Type
hiz_oen
rstob
0
ENABLE
oavalid_lrxd_1
oenb_lrxd_2
50
IO_CELL
octrl_oen
octrl_oen
1
OUT_CELL
51
IO_CELL
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
179
PMC [ PMC-SIERRA, INC ]
