RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
preceding cell. If CELLCRC is logic 0, the contents of the second User
Prepend byte are transported transparently.
DHCS:
The DHCS bit controls the insertion of HCS errors for diagnostic purposes.
When DHCS is set to logic one, the HCS octet for a single cell is inverted
prior to insertion. After the insertion, DHCS is automatically reset to logic 0.
To invert the HCS octet in another cell, DHCS must be set to logic 1 again.
DSCR and HSCR:
The Disable Scramble enable (DSCR) and Header Scramble enable (HSCR)
bits control the scrambling of the cell. When DSCR is logic one, cell header
and payload scrambling is disabled. When DSCR is logic zero, payload
scrambling is enabled and cell header scrambling is determined by HSCR.
HSCR enables scrambling of the System Prepend, User Prepend, User
Header, and HCS byte collectively. The operation of the DSCR and HSCR
bits is summarized below:
DSCR
1
HSCR Operation
X
Cell payload and header scrambling is disabled.
THIS CONFIGURATION SHOULD ONLY BE
USED FOR DIAGNOSTIC PURPOSES.
Cell payload is scrambled. Cell header is left
unscrambled. THIS CONFIGURATION
SHOULD ONLY BE USED FOR DIAGNOSTIC
PURPOSES.
0
0
0
1
Cell payload and header are both scrambled.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
155
PMC [ PMC-SIERRA, INC ]
