欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM7350-PGI 参数 Datasheet PDF下载

PM7350-PGI图片预览
型号: PM7350-PGI
PDF下载: 下载PDF文件 查看货源
内容描述: [Support Circuit, 1-Func, CMOS, PBGA160, 15 X 15 MM, 1.81 MM HEIGHT, PLASTIC, BGA-160]
分类和应用: ATM异步传输模式电信电信集成电路
文件页数/大小: 245 页 / 898 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM7350-PGI的Datasheet PDF文件第103页浏览型号PM7350-PGI的Datasheet PDF文件第104页浏览型号PM7350-PGI的Datasheet PDF文件第105页浏览型号PM7350-PGI的Datasheet PDF文件第106页浏览型号PM7350-PGI的Datasheet PDF文件第108页浏览型号PM7350-PGI的Datasheet PDF文件第109页浏览型号PM7350-PGI的Datasheet PDF文件第110页浏览型号PM7350-PGI的Datasheet PDF文件第111页  
RELEASED  
PM7350 S/UNI DUPLEX  
DATA SHEET  
PMC-1980581  
ISSUE 8  
DUAL SERIAL LINK PHY MULTIPLEXER  
Register 0x03: Miscellaneous Interrupt Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
Unused  
UPFI  
X
X
X
X
X
X
X
X
R
R
R
R
RCSDI  
RBOCI  
ROOLI  
ROOLI:  
The Reference Out of Lock interrupt (ROOLI) status is a logic 1 if the ROOLV  
bit of the Clock Monitor register has changed state since the last time this  
register was read. The ROOLI bit is reset when this register is read.  
RBOCI  
This bit indicates whether there is a pending interrupt for the RXD1, RXD2 Bit  
Oriented Code Status registers. If RBOCI is logic 1, at least one interrupt  
status bit within the RXD1 Receive Bit Oriented Code Status register or the  
RXD2 Bit Oriented Code Status register that has its corresponding enable set  
is a logic 1.  
RCSDI:  
This register indicates whether there is a pending interrupt for the receive  
Clocked Serial Data Interface. If RCSDI is logic 1, at least one interrupt status  
bit within one of the Receive Serial Indirect Channel Interrupt and Status  
register that has its corresponding enable set is a logic 1.  
This bit is cleared upon a read of this register.  
UPFI:  
This bit indicates whether there is a pending interrupt for one of the  
Microprocessor Extract FIFOs. If UPFI is logic 1, at least one interrupt status  
bit within the Microprocessor RXD1 FIFO Interrupt Status register or  
Microprocessor RXD2 FIFO Interrupt Status register that has its  
corresponding enable set is a logic 1.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
92  
 
 复制成功!