RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
REFCLKA:
The REFCLK active (REFCLKA) bit monitors for low to high transitions on the
REFCLK reference clock input. REFCLKA is set high on a rising edge of
REFCLK, and is set low when this register is read.
ROOLV:
The reference out of lock status indicates the clock synthesis phase locked
loop is unable to lock to the reference on REFCLK. ROOLV is a logic one if
the synthesized clock frequency is not within 488 ppm of eight times the
REFCLK frequency.
ROOLE:
The ROOLE bit is an interrupt enable for the transmit reference out of lock
status. When ROOLE and the Master Interrupt Enable bit of the Master
Configuration register are set to logic one, the INTB output is asserted low
when the ROOLV bit changes state.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
95
PMC [ PMC-SIERRA, INC ]
