RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
Register 0x05: Serial Links Maintenance
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RDIDIS2
RDIDIS1
TXDIS2
TXDIS1
MLB2
0
0
0
0
0
0
0
0
MLB1
DLB2
DLB1
DLB1:
The Diagnostic Loopback 1 enable bit allows TXD1+/- data to replace
RXD1+/- data. When DLB1 is logic 1, the receive circuitry for the serial link is
timed off the internal transmit clock and the TXD1+/- data is multiplexed into
RXD1+/- just after the clock recovery. Upstream data is effectively routed to
the downstream datapath if the corresponding high-speed serial link is active.
DLB2:
The Diagnostic Loopback 2 enable bit allows TXD2+/- data to replace
RXD2+/- data. When DLB2 is logic 1, the receive circuitry for the serial link is
timed off the internal transmit clock and the TXD2+/- data is multiplexed into
RXD2+/- just after the clock recovery. Upstream data is effectively routed to
the downstream datapath if the corresponding high-speed serial link is active.
MLB1:
The Metallic Loopback 1 enable bit allows RXD1+/- data to be presented on
TXD1+/-. When LLB is logic one, the sliced receive data replaces the
transmit data at the high-speed transmitter.
Note that the loopback can also be activated remotely through inband bit
oriented codes.
MLB2:
The Metallic Loopback 2 enable bit allows RXD1+/- data to be presented on
TXD1+/-. When LLB is logic one, the sliced receive data replaces the
transmit data at the high-speed transmitter.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
96
PMC [ PMC-SIERRA, INC ]
