RELEASED
PM7350 S/UNI DUPLEX
DATA SHEET
PMC-1980581
ISSUE 8
DUAL SERIAL LINK PHY MULTIPLEXER
TFI:
This register indicates whether there is a pending interrupt for the Transmit
Logical Channel FIFO. If TFI is logic 1, the interrupt status bit in the Transmit
Logical Channel FIFO Interrupt Status register has its corresponding enable
set and is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the Transmit
Logical Channel FIFO Interrupt Status register.
ICIFI
This register indicates whether there is a pending interrupt for the SCI-
PHY/Any-PHY interface input port. If ICIFI is logic 1, at least one interrupt
status bit within the SCI-PHY/Any-PHY Input Interrupt Status register that has
its corresponding enable set is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the SCI-
PHY/Any-PHY Input Interrupt Status register.
OCIFI
This register indicates whether there is a pending interrupt for the SCI-
PHY/Any-PHY Interface output port. If OCIFI is logic 1, at least one interrupt
status bit within the SCI-PHY/Any-PHY Output Configuration and Interrupt
Status register that has its corresponding enable set is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the SCI-
PHY/Any-PHY Output Configuration and Interrupt Status register
UPCIFI:
This bit indicates whether there is a pending interrupt for the Microprocessor
Cell Interface. If UPCIFI is logic 1, at least one interrupt status bit within the
Microprocessor Cell Buffer Interrupt register that has its corresponding enable
set is a logic 1.
This bit is not self-clearing; it is only cleared to logic 0 by reading the
Microprocessor Cell Buffer Interrupt register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
91
PMC [ PMC-SIERRA, INC ]
