S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Figure 25 16 Mbit SDRAM
clock source
SYSCLK
1
CBCSB
CBRASB
CBCASB
CBWEB
CBBS
CKE
CLK
Addr/Ctrl
2 x 2k x 256 x 16
CBA[10:0]
CBDQM
DQM
CBDQ[15:0]
DQ[15:0]
There are three processes, all of which are arbitrated by the SDRAM arbiter, that access the cell
buffer SDRAM:
Sꢀ The RDAT, which reads and writes cell and status information. The granularity of access by
the RDAT is a concatenated 1-cell write, 1-cell read. Either the write or the read may not be
performed, depending on the RDAT’s requirements.
Sꢀ The microprocessor interface, which performs diagnostic reading or writing of 64 bytes of
data. This data is aligned with the cell data. This access is allowed only when the SDRAM
is placed in Diagnostic mode and is provided both to enable SDRAM testing and to
initialize the SDRAM. While it is in diagnostic mode, all regular accesses from the RDAT
are disabled.
Sꢀ The refresh controller, which has a programmable refresh rate.
The SDRAM interface will perform the initialization sequence for the SDRAM. This sequence
is triggered by the SDRAM enable bit in the SDRAM control register. The sequence will
program the SDRAM with a CAS latency of 3, sequential access, write burst mode, and a burst
length of 8. Applications should ensure that sufficient time is provided between SDRAM power
up and when this enable bit is set.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
80
PMC [ PMC-SIERRA, INC ]
