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PM7348 参数 Datasheet PDF下载

PM7348图片预览
型号: PM7348
PDF下载: 下载PDF文件 查看货源
内容描述: [ATM/SONET/SDH IC, CMOS, PBGA324,]
分类和应用: ATM异步传输模式
文件页数/大小: 318 页 / 1736 K
品牌: PMC [ PMC-SIERRA, INC ]
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S/UNI-IMA-4 Telecom Standard Product Data Sheet  
Released  
Channelized  
When channelized links are chosen, the RCAS/TCAS Framing Bit threshold must be configured  
to detect the gap in the clock for the framing bit/byte. This value is dependent upon frame type  
T1/E1, serial clock speed and REFCLK frequency.  
The Link Disable feature may be used when configuring a link to squelch all data from a link  
while it is being provisioned.  
For the Tx direction, the data sent in idle timeslots may be selected with the TCAS Idle Time-  
slot Fill data.  
For T1, all timeslots are used to carry the ATM cell data so all timeslots should be mapped to  
the same virtual link. A one-to-one mapping between physical links and virtual links is  
recommended.  
For E1, timeslots 0 and 16 are used for signaling data and do not contain ATM cell data.  
Therefore, timeslots 1-15 and 17-31 must be mapped and provisioned (enabled) to carry ATM  
cell data. All of the timeslots in a link should be mapped to the same virtual link. A one-to-one  
mapping between physical links and virtual links is recommended.  
For Fractional links, multiple fractional ATM flows may exist on the same physical link. Each  
flow should be mapped to a unique virtual link. There is a limit of 4 virtual links for the S/UNI-  
IMA-4.  
Unchannelized  
Unchannelized is usually used for data streams that are not either T1 or E1 framed. When using  
the unchannelized interface, the user is responsible for providing a clock that has all framing or  
overhead bits gapped out. The S/UNI-IMA-4 receives/sources one bit of data for each clock  
pulse.  
The unchannelized mode allows a wider range of clock frequencies. As the serial line  
frequency increases, the number of links supported decreases.  
Rules for Choosing Clock frequencies  
For up to four lines running at frequencies up to 6.8 MHz each, REFCLK can be from 19.44 to  
33 MHz, SYSCLK can be from 20 to 55 MHz, with the SYSCLK frequency always greater than  
the REFCLK frequency.  
.
/
/
50MHz * Line.Throughput.Mbps  
130Mbps  
SYSCLK(min)= max  
, REFCLK. freq,20MHz  
 
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Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.  
Document No.: PMC-2020889, Issue 2  
270  
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