S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Transmitter
To map the physical link to an ANY-PHY/UTOPIA address, the VPHY address field must be
programmed in the TIMA Physical Link Context Record for the physical link. All other fields
in this table should be cleared to zero. This table may be accessed by the TIMA Indirect
Memory access registers.
To put the physical link into TC mode set the TC_MODE bit in the TXIDCC. This bit may be
accessed by the TXIDCC Indirect Memory Access registers.
Receiver
To map the physical link to an Any-PHY/UTOPIA address, the VPHY address field must be
programmed in the RDAT TC Context Record for the physical link. All other fields in this table
should be cleared to zero. This table may be accessed by the RDAT Indirect Memory access
registers.
To put the physical link into TC mode, set the TC_MODE bit in the RXIDCC. This bit may be
accessed by the RXIDCC Indirect Memory Access registers. Enabling the RXIDCC before the
RDAT Validation Record ensures that the external FIFOs run at empty conditions, as designed.
The RDAT Link Statistics Record, the RDAT TC Group Statistics Record, the RDAT Link
Context Record should also be cleared to zero to reset the statistic counts. The RDAT
Validation Record should be set to TC_MODE.
Set the RDAT_EN bit in the RDAT CONFIGURATION register.
Removing Links from Transmission Convergence Operations
To disable a link in TC mode in the transmitter, the TC_MODE bit in the TXIDCC must be
cleared. To disable a link in TC mode in the receiver, first the RDAT Validation Record should
be cleared, then the TC_MODE bit in the RXIDCC must be cleared. This sequence will ensure
that transient interrupts are not generated.
13.4.3 Configuring For IMA Operations
All IMA timeouts are programmable. The actual timeout period may be one less than the
specified timeout interval, due to the asynchronous nature of events with respect to the timer.
For example, if the interval is 0.25 ns, and the timeout_value is specified as 4, then the timeout
will occur after 0.75 ns to 1.00 ns in that state. To guarantee a timeout of at least 1 second, a
value of 0x5 would have to be written (this is not the register default).
The global IMA interrupt enables default to disabled. In an interrupt driven system, these
interrupt should be selectively enabled in registers 0x218, 0x21A, and 0x21C.
RIPP_EN in Register 0x200 controls whether internal IMA state machines engine is enabled.
This must be set for proper operation.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
274
PMC [ PMC-SIERRA, INC ]
