S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
13 Operation
13.1 Hardware Configuration
The S/UNI-IMA-4 is powered up with the line interface disabled.
The Any-PHY/UTOPIA interface can also be set up in different modes. The Any-
PHY/UTOPIA interface will remain tri-state until configured and the respective
RA_ENABLE/TA_ENABLE bits are set.
13.2 Start-Up
The S/UNI-IMA-4 uses an internal DLL on SYSCLK to maintain low skew on the external
SDRAM interface. When the chip is taken out of hardware reset, the DLL will go into hunt
mode and will adjust the internal SYSCLK until it aligns with the external SYSCLK. The
microprocessor should poll the RUN bit in DLL CONTROL STATUS register until this bit is
set.
At this point the entire chip with the exception of the microprocessor interface and the DLL are
in reset. Before any configuration can be done, including accessing the ram, the chip must be
taken out of software reset by clearing the RESET bit in the Global Reset Register. Once taken
out of reset, the internal ram reset procedure is automatically initiated. The microprocessor
should poll the BIST_DONE bit in the Global Reset register to determine when the internal
RAM reset is complete. While the internal ram is initializing, access to all internal rams is
prohibited, and accesses attempted during this period of time are ignored.
Once the chip is taken out of reset, the external SDRAM should be cleared to all zeros to ensure
no false CRC errors are reported. Access to the SDRAM is through the SDRAM Diagnostic
access port as described in 13.6.1. At this point, the Any-PHY/UTOPIA interface is disabled
and all Any-PHY/UTOPIA outputs are tri-stated. Also, the line side interfaces are disabled and
all internal registers are in their reset state.
13.3 Configuring the S/UNI-IMA-4
13.3.1 Configuring Clock/Data Interface
The Clock/Data interface has 2 major modes, Channelized for E1/T1 traffic and unchannelized
for other traffic types.
Each link should be configured for channelized/unchannelized mode using the RCAS/TCAS
link configuration registers. If configuring channelized links, the T1/E1 mode should be
configured at the same time.
One configured, the links are still disabled. The links must be mapped and provisioned
(enabled)
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
269
PMC [ PMC-SIERRA, INC ]
