S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x046: SDRAM DIAG Indirect Burst Ram Data LSB
Bit
15:0
Type
R/W
Function
BR_DATA_LSB
Default
0
This register should not be written while the BR_BUSY bit is set in the SDRAM Burst RAM
Indirect Access register.
BR_DATA_LSB
The BR_DATA_LSB represents either: (1) the least significant 16 bits of the data to be
written to internal memory or (2) the least significant 16 bits of the read data resulting from
the previous read operation. The read data is not valid until after the BR_BUSY bit has been
cleared.
Register 0x048: SDRAM DIAG Indirect Burst RAM Data MSB
Bit
15:0
Type
R/W
Function
BR_DATA_MSB
Default
0
This register should not be written while the BR_BUSY bit is set in the SDRAM Burst RAM
Indirect Access register.
BR_DATA_MSB
The BR_DATA_MSB represents either: (1) the most significant 16 bits of the data to be
written to internal memory or (2) the most significant 16 bits of the read data resulting from
the previous read operation. The read data is not valid until after the BR_BUSY bit has been
cleared.
The following explains the Burst RAM accessed by the indirect access.
Burst RAM: The microprocessor has access to the external SDRAM for testing and
initialization. There is a 64-byte cell buffer for writing to the external SDRAM and a 64-byte
cell buffer for storing data read from the external SDRAM.
Figure 29 shows the format of the cell in the Burst RAM.
Figure 29 Burst RAM Format
Word #
0x00
0x01
…
31
Bits
0
Burst Write (0)
Burst Write (1)
…
0x0F
0x10
Burst Write(15)
Burst Read (0)
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
120
PMC [ PMC-SIERRA, INC ]
