S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
11.4 SDRAM Registers
Register 0x040: SDRAM Configuration
Bit
Type
Function
Unused
REF_RATE [10:0]
SDRAM_EN
Default
15:12
11:1
0
0
0
0
R/W
R/W
This register configures and enables the SDRAM interface.
SDRAM_EN
The SDRAM_EN enables the SDRAM interface. A transition from 0 to 1 starts the SDRAM
self-initialization procedure. This procedure takes 70 SYSCLK cycles to complete. Note
that no other SDRAM accesses are allowed during this period.
SDRAM_EN is provided to ensure that the power-up of the SDRAM is completed before
the SDRAM self-initialization sequence is started. The power-up time is controlled by
SDRAM_EN. Typically, this must be at least 200 us. When SDRAM_EN = ‘0’, no SDRAM
accesses will occur and the chip will not operate properly.
0) SDRAM accesses are disabled.
1) SDRAM accesses are enabled.
REF_RATE[10:0]
Defines the SYSCLK divide-down factor to determine the SDRAM refresh rate. The
REF_RATE must be configured prior to setting the SDRAM_EN. A zero value will
effectively disable refresh. The value in this register must be programmed to a value greater
than 100 (0x64).
For Example, if the SDRAM requires 4K refreshes in 64 ms with a SYSCLK of 50 MHz,
the REF_RATE should be programmed to:
Sys _Clk
(#_ of _ refresh)
50MHZ
REF _ RATE ꢀ
ꢀ
ꢀ 781 ꢀ 0x30D
4096
ꢀ
ꢁ
64ms
(time_ period)
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
117
PMC [ PMC-SIERRA, INC ]
