S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x044: SDRAM DIAG Burst RAM Indirect Access
Bit
15
14:5
4:0
Type
RO
N/A
Function
BR_BUSY
Unused
Default
0
N/A
0
R/W
BR_ADDR[4:0]
Writing to this register triggers either a write to the Burst Write RAM or a read from the Burst
Read RAM. See 13.6.1 for further details.
BR_ADDR [4:0]
The Burst-ram address (BR_ADDR [4:0]) indicates the RAM address to be configured or
interrogated. The Burst ram is divided into 2 segments: the first is Burst Write RAM, which
is used to store data to be loaded into the External SDRAM; the second is the Burst Read
RAM, which is used to collect data read from the External SDRAM. The access to the
burst-write RAM is always a write operation while the access to the burst-read RAM is
always a read operation. See Figure 29 for the format of the Burst RAM.
o
o
0x00-0x0F: Burst-Write RAM.
0x10-0x1F: Burst-Read RAM.
BR_BUSY
The indirect access command bit (BR_BUSY) reports the progress of an indirect access.
BR_BUSY is set high when the register is written to trigger an indirect access; it will stay
high until the access is complete. Once the access is complete, the BR_BUSY signal is
reset. This register should be polled: (1) to determine when data from an indirect read
operation is available in the SDRAM Indirect Burst RAM Data register or (2) to determine
when a new indirect write operation may commence.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
119
PMC [ PMC-SIERRA, INC ]
