S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x010: Master Interrupt Enable Register
Bit
15:9
8
7
6 :4
3
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Default
0
0
0
0
0
0
0
0
TC_INTR_EN
MISC_INTR_EN
Reserved
ICP_CELL_AVL_EN
RDAT_INTR_EN
TIMA_INTR_EN
RIPP_INTR_EN
The above enable-bits control the corresponding interrupt bits in the Master Interrupt Register.
When an enable-bit is set to a logic 1, the corresponding error event will cause INTB to go
active.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
107
PMC [ PMC-SIERRA, INC ]
