S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x012: Miscellaneous Interrupt Enable Register
Bit
15:5
4
3
2
Type
RO
Function
Unused
Default
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
TC_INTR_FOVR_ERR_EN
SDRAM_CRC_ERR_EN
TX_UTOP_CELLXFERR_EN
TX_UTOP_PAR_ERREN
RX_UTOP_XFR_ERR_EN
1
0
The above enable-bits control the corresponding interrupt bits in the Miscellaneous Interrupt
register. When an enable-bit is set to a logic 1, the corresponding error event will cause the
MISC_INT bit to be set in the Master Interrupt Register.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
108
PMC [ PMC-SIERRA, INC ]
