S/UNI-IMA-4 Telecom Standard Product Data Sheet
Released
Register 0x014: TC Interrupt Enable Register
Bit
15:4
3
2
1
Type
RO
R/W
R/W
R/W
R\W
Function
Unused
HCS_ERR_EN
LCD_ERR_EN
FOVR_ERR_EN
OOCD_ERR_EN
Default
0
0
0
0
0
0
The above enable-bits provide a global enable for the corresponding interrupt bits in the RTTC
Interrupt FIFO. If an enable-bit is not set, the corresponding error event will not cause an entry
to be written into the TC_INTR FIFO. When an enable-bit is set to a logic 1, the corresponding
error event, if enabled for the link, will cause an entry to be written into the TC INTR FIFO.
Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC-2020889, Issue 2
109