Released
Datasheet
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATM Traffic Management Device
9.2.3 Multicast Cell Instance Control Block (Internal Structure)
Base address: xh
For input FIFOS (refer to “AL_RAM_CONFIG” on page 105):
If AL_RAM_CONFIG = 0h, the base address is 206000h (818000h byte).
If AL_RAM_CONFIG = 1h, the base address is 210000h (840000h byte).
If AL_RAM_CONFIG = 2h, the base address is 220000h (880000h byte).
If AL_RAM_CONFIG = 3h, the base address is 250000h (940000h byte).
For output FIFOS:
If AL_RAM_CONFIG = 0h, the base address is 208000h (820000h byte).
If AL_RAM_CONFIG = 1h, the base address is 214000h (850000h byte).
If AL_RAM_CONFIG = 2h, the base address is 214000h (850000h byte).
If AL_RAM_CONFIG = 3h, the base address is 258000h (960000h byte).
Index: 2h
Entry number:
For input FIFOS (refer to “AL_RAM_CONFIG” on page 105):
If AL_RAM_CONFIG = 0h, the entry number is 512.
If AL_RAM_CONFIG = 1h, the entry number is 1K.
If AL_RAM_CONFIG = 2h, the entry number is 1K.
If AL_RAM_CONFIG = 3h, the entry number is 2K.
For output FIFOS:
If AL_RAM_CONFIG = 0h, the entry number is 32.
If AL_RAM_CONFIG = 1h, the entry number is 32.
If AL_RAM_CONFIG = 2h, the entry number is 32.
If AL_RAM_CONFIG = 3h, the entry number is 32.
Type: Read/Write
Byte
Offset
Long
Offset
Read or
Write
Name
Description
0h
0h
MC_HEADER_PTR
R/W (init only) For the input FIFO, this is the OUTCHAN from the
cell. For the output FIFO, this is the pointer to the
entry in the MC header translation table for this entry.
4h
1h
MC_CELL_PTR
R/W (init only) Pointer to the cell buffer containing the multicast cell
to be replicated.
177
PMC [ PMC-SIERRA, INC ]
